Xccela™ consortium

Since the advent of the smart phone, people have become accustomed to and conditioned to expect graphical user interfaces, instant-on responsiveness, 可移植性, constant connectivity, 和更多的 from their modern day electronic devices. 的 expectation is becoming the norm as we cram more 和更多的 smart electronics into our cars, our living spaces, 我们的生活. Meeting the needs of the demanding digital user calls for high-performance system buses for firmware code execution, 数据存储, working data processing, 传感器数据, 和更多的. Current system bus interfaces often result in a tradeoff between performance and footprint: either the high performance of a high pin-count parallel interface or the small active signal footprint of a serial interface.

的 Xccela consortium (link coming soon) is an industry association championed by 微米 to promote the Xccela bus as an open-standard digital interconnect and data communications bus suitable for volatile and nonvolatile memory as well as other types of integrated circuits (for example, 单片机, soc, adc). 的 charter of the consortium is to define the Xccela Bus interface specifications and common command protocols for those devices that will reside and communicate on the Xccela Bus. 的 consortium is open to all companies, including semiconductor manufacturers, systems and electronics companies (customers), and test equipment companies.

In its first iteration, the Xccela Bus is a high-speed, high-performance Octal SPI bus that uses eight data lines for command and data transfer.  的 bus is synchronous and supports both single-transfer rate (STR) operation, where one byte of data is transferred every clock cycle, and dual-data rate (DDR) operation, where two bytes of data are transferred every clock cycle.  的 DDR operation requires the use of a data strobe signal (DQS).  的 Xccela Bus supports clock frequencies up to 200 MHz and data transfer rates up to 400 MB/sec (3.2 Gb /秒).

Interested companies can send their requests to Xccela consortium (link coming soon).